Titanic
Belfast, Northern Ireland
September 5-8, 2022

 


Industrial Keynotes


Keynote Speaker - Sep. 5


Michael Kagan
Chief Technology Officer
NVIDIA

“The 21st century computing

Steve Furber

Michael Kagan is NVIDIA CTO (Chief Technology Officer) since May 2020. He joined NVIDIA through Mellanox acquisition. Michael Kagan was previously Mellanox CTO and a co-founder of Mellanox that was founded in April 1999. From 1983 to April 1999, Mr. Kagan held a number of architecture and design positions at Intel Corporation. While at Intel Corporation, Mr. Kagan was architect of the i860XP vector processor, managed Pentium MMX design, and managed the architecture team of the Basic PC product group. Mr. Kagan holds a BSc. in Electrical Engineering from the Technion — Israel Institute of Technology.

Abstract: From diseases to climate change, AI is helping us solve the worlds complex challenges. but at the same time, high volume complexity growth becomes the new standard for AI models, and it brings an ongoing need for innovative solutions to handle the intense computing demand – both in data centers, at the edge and through the clouds.
With Moore’s Law coming to an end, new approaches such as parallel computing and combining multiple types of accelerated computing takes the stage. And this is exactly where NVIDIA comes in, driving innovation in multiple dimensions in both hardware and software to keep up with the demands of AI. Listen to NVIDIA CTO Michael Kagan talk about Innovation in GPUs, DPUs, CPUs, intra-server interconnect, and networking paired with new data-center architectures and new types of distributed computing. Michael’s keynote will also cover new AI frameworks with more efficient algorithms and AI-optimized software to allow data center performance to run up to 1 million times faster to keep up with AI model complexity.


Keynote Speaker - Sep. 5


David Harold
Chief Marketing Officer
Imagination Technologies

“The Evolution of the IP Industry

Steve Furber

David Harold is responsible for marketing and communications across all Imagination’s business units. He has held communications and marketing management roles at PURE Digital, Cohn & Wolfe, SMI and MAP. He holds a BA in English Literature and an MA in Creative Writing from the University of East Anglia, Norwich, UK. He joined Imagination in 1998. David is a fellow of The Chartered Institute of Marketing.

Abstract: In this keynote Mr. Harold will discuss the emergence of the Semiconductor IP business in the 90s spanning multiple technologies, including CPUs, GPUs, Modems and Interconnect Ips and the decisive role of various companies within the Semiconductor IP ecosystem including Imagination, Arm, Synopsys, Qualcomm, etc. Among others the keynote will explore:
- The forces at play as the IP business takes off with the need for optimization of resources in value chains
- The challenges of the IP business as we know it: the end of Moore’s law
- The emergence of data-based computing with AI/ML and how it augments traditional algorithmic computing
- The emergence of new opportunities in AI/ML and system design for heterogeneous computing
- The pandemic, the tensions East-West and the impact on value chains
- The emergence of the hyperscalers as IP developers
- Impact on key consumer and business segments
- Upcoming trends and challenges, new design strategies and the emergence of the chiplet business
- And the role that Imagination plays in the redefinition of the IP business


Keynote Speaker - Sep. 5


Maximilian Odendahl
Senior Director
AMD

“Flexible ML Compilation for ACAP's AI Engines

Steve Furber

Maximilian Odendahl is on a mission to democratize heterogeneous and adaptive computing, enabling intelligent electronic products of the future. He is currently serving as a Senior Director at AMD, the leader in high performance and adaptive computing, building disruptive developer tools for customers targeting FPGAs, AI Engines and future heterogeneous computing platforms.
He is the former Co-founder and CEO of Silexica leading a stellar team from the spin-off from RWTH Aachen in 2014 until the acquisition by Xilinx in 2021. It served innovative companies in the automotive, robotics, wireless communications, aerospace, and financial industries and had raised $28m from leading international VCs.
Max received a Computer Engineering diploma from RWTH Aachen University in 2010 and was formerly the Chief Engineer of the Chair for Software for Systems on Silicon leading 15 research assistants. His academic research has been published in over 20 publications in international computing conferences and journals. He was selected as Germany's Top 40 under 40 in 2019.

Abstract: AI Engines (AIE) in AMD's ACAP devices are a powerful, domain-specific array of programmable and adaptable VLIW SIMD cores that enable breakthrough AI inference acceleration. AIEs offer AI-optimized instructions and native datatypes as well as tightly coupled memories and specialized data movers that allow implementing optimal dataflow-style compute structures. To exploit the AIE's HW architectural advantages for AI workloads, we are building an MLIR-based compiler that starts from customer-defined ONNX models and performs several optimizing transformations, such as tiling and layer fusion, until generating an optimal dataflow design and SW binaries for the AIE. This presentation gives an overview of our flexible ML compiler for ACAP's AIE. 


Keynote Speaker - Sep. 6


Daniel O'Loughlin
Vice President Engineering
Qualcomm Technologies Inc. 

Security: The Second Wave of Convergence

Steve Furber

Over the last eight years, Dan has provided SoC HW and IP security leadership across Mobile, Auto and IoT Business Units at Qualcomm. Today Dan leads global SoC Security teams across Engineering, Architecture and Evaluation development domains at Qualcomm.  Prior to 2014, Dan held security leadership roles at Cryptography Research Inc./Rambus, where he worked on security silicon IP, software and infrastructure, and Certicom/Blackberry, where he led security hardware development teams in the U.S. and Canada.

Abstract: During the 1990's the introduction of the internet, web browser, email and resulting electronic services led to an initial commercialization wave of crypto and security technologies. During this time security technology evolved from serving the needs of government and military to solving problems in the public domain. This disruptive convergence led to new security innovations and wide adoption of security technologies in the public domain. With the emergence of 5G, and the age of hyper-connectivity, a second wave of disruptive convergence is upon us. That second wave is defined by the hyper-connectivity of devices resulting in the adoption of these devices into high value services and deeply embedded into mission critical applications. The consequence from hyper-connectivity with respect to security risk and liability is having significant impact on the SoC industry. In addition, today’s geo-political landscape is driving regional regulatory requirements that are serving to drive global fragmentation and challenge security interoperability and scale needed to protect consumers. Today we will discuss the impact these forces are having on the future direction of SoC security technology.


Main Conference Keynotes


Keynote Speaker - Sep. 6


Steve Furber
ICL Professor of Computer Engineering
Department of Computer Science, University of Manchester, UK.

“From ARMs to Brains

Steve Furber

Steve Furber CBE FRS FREng is ICL Professor of Computer Engineering in the Department of Computer Science at the University of Manchester, UK. After completing a BA in mathematics and a PhD in aerodynamics at the University of Cambridge, UK, he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor. Over 200 billion ARM-powered chips have since been manufactured, powering much of the world's mobile and embedded computing. He moved to the ICL Chair at Manchester in 1990 where he leads research into asynchronous and low-power systems and, more recently, neural systems engineering, where the SpiNNaker project has delivered a computer incorporating a million ARM processors optimised for brain modelling applications.

Abstract: Starting from humble origins in the early 1980s at Acorn Computers, a small UK home company, the ARM (then ‘Acorn RISC Machine’) microprocessor has gone on to dominate mobile computing and features in a wide range of other applications from the world’s fastest supercomputer to datacentres to edge AI applications. One such application is SpiNNaker, the world’s largest neuromorphic computing platform, that was built to accelerate understanding of the brain and thereby bring new brain-inspired concepts to AI.


Keynote Speaker - Sep. 6


Máire O'Neill
Regius Professor in Electronics and Computer Engineering,
Director, ECIT,  Director, CSIT
Queen's University Belfast

“Machine Learning and Hardware Security

Leef

Professor Máire O’Neill, OBE, FREng, has a strong international reputation for her research in hardware security and applied cryptography. She is Regius Professor in Electronics and Computer Engineering. She is Director of the Institute of Electronics, Communications and Information Technology (ECIT) and Director of the Centre for Secure Information Technologies (CSIT), QUB. She is also Director of the £5M UK-wide Research Institute in Secure Hardware and Embedded Systems (RISE: www.ukrise.org) and is a member of the UK AI Council. She has received numerous awards which include a Blavatnik Engineering and Physical Sciences medal, 2019, a Royal Academy of Engineering Silver Medal, 2014 and British Female Inventor of the Year 2007. She has authored two research books and over 175 peer-reviewed conference and journal publications. She is a Fellow of the Royal Academy of Engineering, a member of the Royal Irish Academy and Fellow of the Irish Academy of Engineering.

Abstract: With the globalisation of supply chains the design and manufacture of today’s electronic devices are now distributed worldwide, for example, through the use of overseas foundries, third party intellectual property (IP) and third party test facilities. Many different untrusted entities may be involved in the design and assembly phases and therefore, it is becoming increasingly difficult to ensure the integrity and authenticity of devices. The supply chain is now considered to be susceptible to a range of hardware-based threats, including hardware Trojans, IP piracy, reverse engineering, IC cloning and side-channel attacks. These attacks are major security threats to military, medical, government, transportation, and other critical and embedded systems applications. This talk will explore the role machine learning has to play in hardware-based threats and in improving hardware security.


Keynote Speaker - Sep. 7


David Patterson
Distinguished Engineer, Google, and
Pardee Professor of Computer Science, Emeritus
University of California at Berkeley

“A Decade of Machine Learning Accelerators: Lessons Learned and Carbon Footprint

Leef

David Patterson was a Professor of Computer Science at the University of California at Berkeley, which he joined after graduating from UCLA. He retired after 40 years and became a Distinguished Engineer at Google in 2016.
He is working on domain-specific computer architectures for machine learning. He is also Google’s representative and on the Board of Directors of the RISC-V Foundation, whose goal is to make the free and open RISC-V instruction set architecture as popular for hardware as Linux is for operating systems.
Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of researchers to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. The best-known projects were Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW), each of which helped lead to billion dollar industries.
A measure of the success of projects is the list of awards won by Patterson and as his teammates: the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, the ACM-IEEE Eckert-Mauchly Award, and the Katayanagi Prize. He was also elected to both AAAS societies, the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and to be a Fellow of the Computer History Museum. The full list includes about 35 awards for research, teaching, service, and outreach.
In his spare time he coauthored six books, including two with John Hennessy. He also served as Chair of the Computer Science Division at UC Berkeley, Chair of the Computing Research Association, and President of the Association for Computing Machinery (ACM).

Abstract: The success of deep neural networks (DNNs) from Machine Learning (ML) has inspired domain specific architectures (DSAs) for them. ML has two phases: training, which constructs accurate models, and inference, which serves those models. Google’s first generation DSA offered 50x improvement over conventional architectures for inference in 2015. Google next built the first production DSA supercomputer for the much harder problem of training. Subsequent generations greatly improved performance of both phases. We start with ten lessons learned, such as DNNs grow rapidly; workloads quickly evolve with DNN advances; the bottleneck is memory, not floating-point units; and semiconductor technology advances unequally.
The rapid growth of DNNs rightfully raised concerns about their carbon footprint. The second part of the talk identifies the “4Ms” (Model, Machine, Mechanization, Map) that, if optimized, can reduce ML training energy by up to 100x and carbon emissions up to 1000x. By improving the 4Ms, ML held steady at <15% of Google’s total energy use despite it consuming ~75% of its floating point operations. Climate change is one of our most important problems,so ML papers should include emissions explicitly to foster competition on more than just model quality. External estimates have been off 100x–100,000x, so publishing emissions also ensures accurate accounting, which helps pinpoint the biggest challenges. With continuing focus on the 4Ms, we can realize the amazing potential of ML to positively impact many fields in a sustainable way.


Conference Dinner speech


Conference Dinner Speaker - Sep. 6


Lynn Conway
Professor of Electrical Engineering and Computer Science, Emerita
University of Michigan

“Surfing the waves of techno-social evolution”

Steve Furber

After earning her BS and MSEE from Columbia University, Lynn joined IBM Research in 1964, where she made foundational contributions to computer architecture.
Joining Xerox Palo Alto Research Center in 1973, Lynn invented powerful methods for silicon chip design, was principal author of the seminal text Introduction to VLSI Systems, and pioneered the teaching of the methods at MIT – thereby launching a world-wide revolution in microelectronic design in the late 1970’s.
Lynn also invented e-commerce infrastructure for rapid chip-prototyping, spawning the modern "fabless design" plus "silicon foundry" industrial model for semiconductor design and fabrication. As Assistant Director for Strategic Computing at DARPA, Lynn then led the Defense Department’s 1980's effort to evolve the US technology-base for microelectronic-based intelligent weapons systems.
Lynn joined the University of Michigan in 1985 as Professor of EECS and Associate Dean of Engineering, where she continued her distinguished career. In 2012, Lynn published her “VLSI Reminiscences”, finally revealing how – hidden behind the scenes – she conceived the ideas and orchestrated the events that shaped a vital global industry.
Lynn has received many awards for her work, including election to the National Academy of Engineering and honorary doctorates from Trinity College, Illinois Institute of Technology, the University of Victoria and the University of Michigan.
In 2015 Lynn received the James Clerk Maxwell Medal from the IEEE and the Royal Society of Edinburgh. Her citation includes these words: “Lynn Conway’s work has provided the underpinnings for innovations, discoveries and achievements in every area of scientific and humanitarian study.”

Abstract: When we imagine doing adventurous engineering out into new territory, it’s fun to mentally-reenact the journeys of earlier explorers – to learn what they did and how they did it – and pattern on them.
Think how the rapid spread and use of moveable-type printing in the mid-1400s escalated the Renaissance, how the daring coordinated use of compass, astrolabe and seaworthy ships in the 1500s triggered the age of exploration, and how the co-evolution of the railroads and telegraphy in the mid 1800’s exponentiated the industrial revolution.
Think of all the human roles and experiences during those bursts of “techno-social evolution”, and of the adventures of early surfers of such big waves. By doing so, we can get “outside the bubble” and envision our own embedded, entangled roles in such waves of change.
Centuries from now, archeologists will unearth massive world-wide evidence of an era when humans designed and printed ever-more-powerful electronic machinery onto tiny chips of Silicon, and used them to intelligently animate a vast landscape of innovative techno-social systems.
As they ponder the tracks our clans left behind, they’ll try to imagine how we all did what we did. Meanwhile, we get to live the grand adventure of surfing a “really big one”!

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