September 3-6, 2019
Marina Bay Sands Hotel

List of Accepted Regular Papers:

0.8 BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique

Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN)

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

A Glitch Key-Gate for Logic Locking

Reconfigurable Routing Paths as Noise Generators Using NoC Platform for Hardware Security Applications

EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT Using Stationary Neuromorphic Vision Sensors

A Novel Test Vector Generation Method for Hardware Trojan Detection

RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC

Power and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing

Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs

A Network on Chip Adapter for Real-Time and Safety-Critical Applications

Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms

Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs

Loop Optimization of MGS-QRD Algorithm for FPGA High Level Synthesis

Crosstalk-aware TSV-buffer Insertion in 3D IC

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications

Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors

Voltage Stacked Design of a Microcontroller for near/sub-threshold Operation

Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks Using Geometric Programming

ML-based Reinforcement Learning Approach for Power Management in SoCs

A BJT-Based Temperature Sensor in 40 nm CMOS with ±0.8°C (3Σ) Untrimmed Inaccuracy

A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications

A 45 Gb/s, 98 fJ/bit, 0.02 Mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-Nm CMOS

A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection

A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-Nm CMOS

A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications

Group Delay Compensation by Combining 3-Tap FFE with CTLE for 80Gbps-PAM4 Optical Transmitter

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier

Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits

A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18Um SiGe BiCMOS Technology

A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications

Error-latency Trade-Off for Asynchronous Stochastic Computing with Sigma-Delta Streams for the IoT

Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function

A 10-Bit Area-efficient Source Driver for Printed OLED Display

List of Accepted Poster Papers:

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises

Hardware Obfuscation of AES IP Core Using Combinational Hardware Trojan Circuit

Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration

Establishing Cyber Resilience in Embedded Systems for Securing Next-Generation Critical Infrastructure

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images

Accelerating Binary-Matrix Multiplication on FPGA

LIGHTER-R: Optimized Reversible Circuit Implementation for SBoxes

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks

Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs

Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers

Current-Reuse LC Divide-by-8 Injection-Locked Frequency Divider

A 90µW, 2.5GHz High Linearity Programmable Delay Cell for Signal Duty-Cycle Adjustment

A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL

Analysis and Modeling of Passive LC Filters Using Node Elimination Technique

A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

DiaNet: An Efficient Multi-Grained Reconfigurable Neural Network in Silicon

Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip

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