CTO, System-Technology Co-Optimization (STCO) Division, IMEC, Belgium, and
Professor, EECS Dept, University of California at Berkeley
Jan Rabaey is a Professor in the Graduate School in the EECS Department at the University of California at Berkeley, where he held of the Donald O. Pederson Distinguished Professorship for over 30 years before retiring. Before joining the faculty at UC Berkeley, he was a research manager at IMEC from 1985 until 1987. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has served as the Electrical Engineering Division Chair at Berkeley twice. In 2019, he also became the CTO of the System-Technology Co-Optimization (STCO) Division of IMEC, Belgium.
Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, low power integrated circuits, mobile devices, sensor networks, and ubiquitous computing. His current focus is of the interaction between the cyber and the biological world (amongst many other things.
He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, the Semiconductor Industry Association (SIA) University Researcher Award, and the SRC Aristotle Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received a number of honorary doctorates. He has been involved in a broad variety of start-up ventures.
Abstract: The world as we know it is going through some major upheavals: climate change, pandemics and technology-induced societal changes are upsetting our world-picture with no real end in sight. Hence, an extremely relevant question is how ‘we humans’ are going to cope with this rapid evolution. One plausible answer is for us to use those same technologies to evolve ourselves, and to equip us with the necessary tools to interact with, survive, and prosper in spite of (or in light of) these changes.
Various wearable devices have been or are being developed to do just that. However, their potential to create a whole new set of human experiences is still largely unexplored. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. In this presentation, we focus on the computational aspects of such an intranet, tasks that are complicated by the extreme energy and form-factor limitations imposed on the wearable (or implanted) devices. An important aspect is that the human intranet should not only be able to learn from experience, but capable of dealing with changes in both the environment and in itself. Moreover, it should be able to do so on a continuous base. Computational models, architectures and circuits that enable such capabilities at ultra-low energy and small form factor are hence needed. A glimpse of what may be possible will be presented.
Edward G. Tiedemann Jr. Distinguished Professor, and Director C-BRIC
Purdue University, West Lafayette, IN
“Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems”
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 25 patents, supervised 91 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).
Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Desoer Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
Abstract: Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional "von-Neumann" architectures are several orders of magnitude more area and power expensive than the biological brain. Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of ‘data deluge’ and emergent data-centric applications. Exploring the new paradigm of computing necessitates a multi-disciplinary approach:exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations of the brain leading to a better match between the hardware substrate and the model of computation. In this talk, I will focus on our recent works on neuromorphic computing with spike based learning and the design of underlying hardware that can lead to quantum improvements in energy efficiency with good accuracy.