September 5-8, 2017
Hotel Novotel München City
Munich, Germany

Wednesday Keynote Speaker


Gerd Teepe
Director, Design Enablement

Globalfoundries

22 and 12 nm FDSOI vs. FINFET for SoC development”

Gerd TeepeGerd Teepe is director of Dresden Design Enablement of GLOBALFOUNDRIES. He graduated from the RWTH Aachen University (Dipl. 1982, PhD. 1986). He then worked on fault tolerant microprocessors at the NEC-Central-Research-Laboratories, Tokyo, Japan. For Motorola-Semiconductors in Europe, Teepe held various engineering and management positions in design, marketing and product-operations. Gerd Teepe joined AMD in Dresden in 2004 and is part of GLOBALFOUNDRIES since its foundation in 2009.

Abstract: 


Wednesday Keynote Speaker


Ron Martino
Vice President, i.MX Application Processor Product Line
NXP Semiconductors, Austin, TX, USA
 

Quad core SoC in FDSOI technology”

Ron Martino

Ronald M. Martino is the Vice President of i.MX Application Processor Business and Advanced Technology Adoption at NXP Semiconductors. He is responsible for driving the broad adoption and rapid growth of the i.MX application processor business across consumer, industrial and automotive applications. Prior to this, he was Vice President of Product Development and Hardware R&D for Freescale’s Automotive MCU Product Group,  responsible for the development of Freescale’s Auto microcontrollers designs and product introductions. Before this, he was Vice Chairman of the Freescale Qiangxin IC Design Company based in Tianjin, China in addition to Vice President of Freescale’s worldwide microcontroller R&D organization responsible for development of both automotive and general market embedded processing solutions.
Ron joined Freescale in February 2008 from IBM, where he was director of Power Architecture offerings. He worked at IBM for 20 years with a focus on high-performance computing, networking, RF communication, and gaming microelectronics.
At IBM, Ron was Director of Power Architecture processor and licensing business focused on 32-bit and 64-bit MPUs from 2003 to 2008. Ron also served as Director of IBM’s ASIC and Core IP development organization, manager of IBM’s RF product introduction organization, and manager of an advanced technology support team from 1995 through 2002. Throughout this period, Ron also had assignments focused on strategic customer relationship management and gross margin enhancements. Prior to this, Ron held multiple engineering roles in advanced technology research and development.

Abstract:


Thursday Keynote Speaker


to be announced


Thursday Keynote Speaker


Josef Hausner
Division Vice President R&D IP Strategy,
Intel Mobile Communications, Germany

The Path to Global Connectivity – Wireless Communication enters the Next Generation

Josef Sep2016 1 smallJosef Hausner is responsible for the architecture evolution of Intel’s cellular modems covering wireless standards ranging from GSM, 3G, LTE, Cellular IoT standards like NB-IOT, to 5G. Josef joined Intel in 2011 with the acquisition of Infineon’s Wireless division where he was Vice President Concept Engineering defining cellular and connectivity products including algorithms, chip architectures, as well as complete SoCs and platforms. In 2004 Josef became a Full Professor for Integrated Systems at Ruhr-Universität-Bochum, researching on Integrated Systems and Circuits for Multi-Standard Wireless Communications, speaking and chairing sessions and symposia at conferences as well as at technical and industrial fora.

Josef holds a Dr.-Ing. Degree in the field of microwave technology from the Technische Universität in Munich. He is a member of the IEEE, VDE, and the Informationstechnische Gesellschaft (ITG), serves as curator of the Fraunhofer Heinrich Hertz Institute (HHI) and is elected board member of the ITG Germany.

Abstract:As mobile broadband (MBB) technologies evolve, devices need to support increasing bandwidth with multiple frequencies and dramatically exploding data rates. New air interfaces in 5G will show once again the gain in data rates as we have seen from 2G, to 3G to HSPA, to LTE and LTE advanced. These technologies in a single device provide the best possible services with great user experience to all people no matter where they are.  Developing the next generation takes advantage of higher density in analog and digital silicon circuitry to enable low cost high performance solutions.
Next to those MBB systems, massive and reliable machine-type communications – also known as the Internet of Things – will get developed under the umbrella of 5G technologies. This talk will elaborate on challenges of related radio and semiconductor technologies, and highlight architectural breakthroughs to enable next generation solutions for global connectivity.


Friday Plenary Speaker


Norbert Wehn
Chair for Microelectronic System Design,
University of Kaiserslautern, Germany

The Memory Challenge in Computing Systems: a Survey”

WehnNorbert Wehn holds the chair for Microelectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has more than 300 publications in various fields of microelectronic system design and holds several patents. Two start-ups spinout of his research group. In 2003 he served as program chair for DATE 2003 and as general chair for DATE 2005 respectively. In 2014 he was general Co-Chair of FPL 2015. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power techniques, advanced SoC architectures, 3D integration, memory subsystems, reliability issues in SoC and hardware accelerators for financial mathematics and big data applications

Abstract: It is well known that DRAM memory performance cannot keep pace with the performance of today’s multicore compute systems. In addition to the memory bandwidth problem, there is another major challenge, namely, the power/energy challenge. DRAMs are largely contributing to the overall power consumption. Thus, there is a need for power and bandwidth optimization of the DRAM memory subsystems. Moreover, new memory architectures are emerging like HBM, HMC and Wide I/O DRAMs to cope with the increasing bandwidth requirements. In this talk, we will give an overview on these new architectures and present various optimization techniques to optimize bandwidth and energy consumption in DRAM based memory systems.


Banquet Speaker


to be announced


 

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