Congratulations to the authors of the following accepted papers! 

Each of the submission has received either 4 or 5 reviews. Many thanks to our TPC members. Detailed reviews, camera-ready preparation, registration information, etc. will come soon. 

Regular papers:

Design Method for Delta-Sigma Force-Feedback Accelerometer Interface Systems 

Hybrid Stochastic Computing Circuits in Continuous Statistics Domain 

Dynamic Supply and Threshold Voltage Scaling Towards Runtime Energy Optimization over a Wide Operating Performance Region

Dynamic Precision Multiplier for Deep Neural Network Accelerators 

A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks 

HARDY: Hardware Based Analysis for malwaRe Detection in Embedded sYstems 

A General Purpose Single-Slope MEMS Capacitive Sensors Interface Circuit for IoT Applications 

A Sub-1 ppm/°C CMOS Bandgap Voltage Reference with Process Tolerant Piecewise Second-Order Curvature Compensation 

A Dynamic Expansion Order Algorithm for the SAT-based Minimization 

A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity 

A SpaceWire PHY with Double Data Rate and Fallback Redundancy 

Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA

A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security

Optimizing CNN Accelerator with Improved Roofline Model 

Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA 

Fine Grained Control Flow Checking with Dedicated FPGA Monitors 

Holistic 2.5D Design Flow: A 65Nm Shared-Block Microcontroller Case Study 

Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer 

Evolution of Embedded Platform Security Technologies: Past, Present & Future Challenges

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs 

End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms Detection 

Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs 

A Low-Cost Fault Injection Attack Resilient FSM Design

Poster Papers:

Improving the Performance of a NoC-based CNN Accelerator with Gather Support 

The IANET Hardware Accelerator for Audio and Visual Data Classification

An Inverter-based On-Chip Voltage Reference Generator for Low Power Application

Downlink-Centric User Scheduling for Full-Duplex MU-MIMO Systems

DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations

Mist-Scan: A Secure Scan Chain in Cryptographic Chips to Resist Scan-Based Attacks

A High-Speed Architecture for the Reduction in VDF Based on a Class Group

Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency 

Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN 

An Energy-Efficient Low Power LSTM Processor for Human Activity Monitoring

A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware

Design Tracks:

Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC

Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC Using Machine Learning 

IMPORTANT COVID-19 Update - June 3, 2020

The COVID-19 pandemic has altered our research community in countless ways. How we gain knowledge, conduct research, socialize with peers, and interact with the community are all affected.

The safety and well-being of the attendees are our top priorities. In view of the uncertainties surrounding the COVID-19 situation, we have decided to change SOCC2020 into a full virtual event. The conference dates, Sept. 8-11, will remain the same. The paper review and acceptance process will proceed as planned. Please note that we have extended the submission deadline to June 5, which will be a hard deadline.

We encourage you to submit your latest unpublished research work to SOCC. Registering your paper will serve as notice of intent to participate and to submit your full paper until June 5. Thank you for your patience and cooperation as we navigate these new conferencing challenges.

Stay tuned for news on substantially reduced registration fees and other organization details.

Systems-on-Chip for the next decade

Multibillion transistor System on Chip (SoC) devices, comprised of digital, analog, RF, optical, and Micro-Electro-Mechanical Systems (MEMS), are integral parts of ubiquitous communication, computing, entertainment, medical, logistics and carrier products. SoC has been the enabling technology and main thrust behind the evolution of the Internet into a global, cloud based communication and economic paradigm. Recent advances in systems, deep-submicron, nano process, and quantum-based technology are unleashing new opportunities, and also new challenges. These challenges include managing design and verification complexity, EDAtools, on-chip communication, design reuse, handling inevitable faults, and the efficient integration of emerging MEMS and nano components into next generation SoCs.

For more than 30 years the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for sharing the latest advancements in SoC architecture, systems, logic and circuit design, process technology, test, design tools, and applications. We proudly continue this tradition with the 2020 conference.

The 33^rd SOCC offers a three-day technical program including keynote and plenary speeches, oral and poster presentations, hot-topic panel sessions, and tutorials held by experts in the field. In addition, SOCC has a long tradition of high-class social events complementing the technical program, helping you to discuss your work with your colleagues, and enhancing your professional network.

For the first time in its history, SOCC will be held as a fully virtual, on-line event, with a mixture of pre-recorded presentations and live sessions.