Keynote Speakers

Wolfgang Furtner
Wolfgang FurtnerDistinguished Engineer for SoC Architectures
Infineon Technologies AG
Wolfgang Furtner is a Distinguished Engineer for SoC Architectures at Infineon Technologies AG. He received his degree in Electrical Engineering from the University of Applied Sciences Munich, Germany. He is heading the System Concept Engineering for power and sensors. His interests are Embedded Architectures for Artificial Intelligence and Machine Learning, Smart Sensors and System Architectures for Quantum Computing.

SoC Architecture for the Edge

The architecture of Integrated Circuits is changing rapidly with denser process nodes and more-than-moore type of integration. In particular for edge processing and IoT tight integration with sensors at lowest possible power is imperative. SoCs are becoming increasingly software defined demanding hardware/software co-design and virtual prototyping. Open source standards and IP play an increasing role in chip design while it still remains key to safeguard IP quality and maintenance. Modern embedded computing platforms need to accelerate latest neural network architectures. Beyond that new computing paradigms such as neuromorphic and in-memory computing are seeking their application.

Norbert Wehn
Norbert WehnChair for Microelectronic System Design
University of Kaiserslautern-Landau
Norbert Wehn holds the chair for Microelectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern-Landau. He has more than 500 publications in various fields of microelectronic system design and holds several patents. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power techniques, advanced SoC and memory architectures, postquantum cryptography, reliability challenges in SoC, machine learning, IoT and smart learning environments.
Harald Kroeger
Harald KroegerMember of the Board, Head of Sales, and President of Automotive
Harald Kroeger is a member of the board, head of sales, and president of automotive for since Jan 2023.
Harald was a member of the board of Tesla and or Rivian.
Mr. Kroeger served as a member of the board of management for Bosch until Dec 2021, being responsible for all of automotive besides powertrain, 25 bn of business and a 100thsd people reporting to him.
Before that, he was 21 years with Mercedes-Benz, where in his career he was -amongst others- head of purchasing for electrics/electronics, head of quality, and head of development for electrics and electronics of Mercedes-Benz cars.
Mr. Kroeger holds an M.S. in Electrical Engineering from Stanford University, and he holds a Diplom-Engineer in Control Engineering and a Bachelor in Economics, both from the University of Hannover.
Lana Josipović
Lana JosipovićAssistant Professor, Department of Information Technology and Electrical Engineering
ETH Zurich
Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in 2022, she received a Ph.D. in Computer Science from EPFL. Her research interests include reconfigurable computing and electronic design automation. She is an Associate Editor for IEEE TCAD and ACM TRETS, and served as general, program, and topic chair of several international conferences and workshops. She is a recipient of the EDAA Outstanding Dissertation Award, EPFL Doctorate Award, Google Ph.D. Fellowship in Systems and Networking, Google Women Techmakers Scholarship, and Best Paper Award at ISFPGA'20.

From Software Programs to Digital Circuits

High-Level Synthesis (HLS) compilers enable programmers to automatically generate hardware designs from high-level software abstractions instead of writing tedious and time-consuming low-level hardware descriptions. However, today’s HLS compilers are still accessible only to expert users and for particular classes of applications; generating good-quality circuits still requires peculiar code restructuring and extensive experimentation with the tools. In this talk, I will discuss the challenges and limitations of current HLS approaches. I will outline an alternative HLS technique that overcomes these limitations and achieves high parallelism in general-purpose software applications. Finally, I will share my vision on future advancements of HLS and hardware design.

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