SoC Architecture for the Edge

The architecture of Integrated Circuits is changing rapidly with denser process nodes and more-than-moore type of integration. In particular for edge processing and IoT tight integration with sensors at lowest possible power is imperative. SoCs are becoming increasingly software defined demanding hardware/software co-design and virtual prototyping. Open source standards and IP play an increasing role in chip design while it still remains key to safeguard IP quality and maintenance. Modern embedded computing platforms need to accelerate latest neural network architectures. Beyond that new computing paradigms such as neuromorphic and in-memory computing are seeking their application.

It’s all About Energy Efficiency

Energy efficiency is becoming one of the most critical metrics in microelectronic systems. Although transistor density continues to follow Moore’s Law, improvements in power consumption and delay have significantly slowed down. This presents substantial challenges for efficient architectures, leading to the development of new computing paradigms such as in-memory computing. In this talk, we will explore the energy efficiency challenges in two distinct application domains. Firstly, AI applications are extremely data-hungry, with off-chip memory access constituting a major portion of their overall energy consumption. Hence, we will focus on the memory aspect and present various optimizations and Processing-In-Memory (PIM) concepts to improve energy efficiency. In the second part, we will shift our focus to 5G/6G digital baseband processing and demonstrate how cross-layer design can significantly improve energy efficiency.

From Software Programs to Digital Circuits

High-Level Synthesis (HLS) compilers enable programmers to automatically generate hardware designs from high-level software abstractions instead of writing tedious and time-consuming low-level hardware descriptions. However, today’s HLS compilers are still accessible only to expert users and for particular classes of applications; generating good-quality circuits still requires peculiar code restructuring and extensive experimentation with the tools. In this talk, I will discuss the challenges and limitations of current HLS approaches. I will outline an alternative HLS technique that overcomes these limitations and achieves high parallelism in general-purpose software applications. Finally, I will share my vision on future advancements of HLS and hardware design.

Hardware Alchemy for Machine Learning Acceleration

Machine learning is fueling a new hardware revolution. CPU, GPU, and FPGA manufacturers, and even memory and storage companies, are all in a race to create specialized hardware that accelerates machine-learning tasks. Even major machine-learning service providers like Google and Amazon are developing their own hardware solutions.

Next-generation cyber-physical systems, such as self-driving cars, rely heavily on machine-learning for perception, requiring real-time performance that demands hardware acceleration.

However, acceleration means different things in different contexts. This can be seen in the contour of various emerging solutions. This talk will explore the common denominators across various machine learning techniques and how hardware is being leveraged to accelerate them today.

Enabling an Open Eco-System for Chiplet based Automotive SoCs

The automotive industry is currently witnessing an unprecedented surge in performance demands, surpassing the limitations set by Moore's Law. This surge can be attributed to several key factors, including the evolution of software-defined vehicles marked by centralized architectures and a heightened level of functional integration. Additionally, advancements in assisted and automated driving technologies have propelled the industry forward. Notably, the escalating demand for an enriched customer experience within the automotive sector has become a driving force behind the need for increased performance.

With the every-increasing performance demands of automotive, the integration of Chiplets-Based System-on-Chip (SoC) is emerging as a tangible reality. Traditional approaches, such as board-level integration (involving the integration of smaller specialized SoCs on a single PCB) and chip-level integration (constructing more advanced monolithic SoCs), are encountering inherent limitations. Now a pivotal question arises concerning the role of chiplets in the automotive context: Will they be closed vendor-specific or open up to a diverse, multi-supplier ecosystem?

The window of opportunity to shape the future of Automotive System-on-Chip (SoC) is now. Immediate actions are necessary to open automotive high performance SoCs designs for innovation and differentiation. Lowering entry barriers for new market innovations is essential, as is enabling scalability in the development of System-on-Chip (SoC). Defining standards for system behavior becomes crucial to improving interoperability, ensuring a comprehensive automotive life cycle. Moreover, fostering a market with multiple suppliers is integral for enhancing diversity and fostering healthy competition. Strategic approach - Embracing the Chiplet Advantage We propose to proactive embrace and shape the future of chiplets in automotive.