Keynote Speakers

Wolfgang Furtner
Wolfgang FurtnerDistinguished Engineer for SoC Architectures
Infineon Technologies AG
Wolfgang Furtner is a Distinguished Engineer for SoC Architectures at Infineon Technologies AG. He received his degree in Electrical Engineering from the University of Applied Sciences Munich, Germany. He is heading the System Concept Engineering for power and sensors. His interests are Embedded Architectures for Artificial Intelligence and Machine Learning, Smart Sensors and System Architectures for Quantum Computing.

SoC Architecture for the Edge

The architecture of Integrated Circuits is changing rapidly with denser process nodes and more-than-moore type of integration. In particular for edge processing and IoT tight integration with sensors at lowest possible power is imperative. SoCs are becoming increasingly software defined demanding hardware/software co-design and virtual prototyping. Open source standards and IP play an increasing role in chip design while it still remains key to safeguard IP quality and maintenance. Modern embedded computing platforms need to accelerate latest neural network architectures. Beyond that new computing paradigms such as neuromorphic and in-memory computing are seeking their application.

Norbert Wehn
Norbert WehnChair for Microelectronic System Design
University of Kaiserslautern-Landau
Norbert Wehn holds the chair for Microelectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern-Landau. He has more than 500 publications in various fields of microelectronic system design and holds several patents. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power techniques, advanced SoC and memory architectures, postquantum cryptography, reliability challenges in SoC, machine learning, IoT and smart learning environments.

It’s all About Energy Efficiency

Energy efficiency is becoming one of the most critical metrics in microelectronic systems. Although transistor density continues to follow Moore’s Law, improvements in power consumption and delay have significantly slowed down. This presents substantial challenges for efficient architectures, leading to the development of new computing paradigms such as in-memory computing. In this talk, we will explore the energy efficiency challenges in two distinct application domains. Firstly, AI applications are extremely data-hungry, with off-chip memory access constituting a major portion of their overall energy consumption. Hence, we will focus on the memory aspect and present various optimizations and Processing-In-Memory (PIM) concepts to improve energy efficiency. In the second part, we will shift our focus to 5G/6G digital baseband processing and demonstrate how cross-layer design can significantly improve energy efficiency.

Harald Kroeger
Harald KroegerMember of the Board, Head of Sales, and President of Automotive
SiMa.ai
Harald Kroeger is a member of the board, head of sales, and president of automotive for SiMa.ai since Jan 2023.
Harald was a member of the board of Tesla and or Rivian.
Mr. Kroeger served as a member of the board of management for Bosch until Dec 2021, being responsible for all of automotive besides powertrain, 25 bn of business and a 100thsd people reporting to him.
Before that, he was 21 years with Mercedes-Benz, where in his career he was -amongst others- head of purchasing for electrics/electronics, head of quality, and head of development for electrics and electronics of Mercedes-Benz cars.
Mr. Kroeger holds an M.S. in Electrical Engineering from Stanford University, and he holds a Diplom-Engineer in Control Engineering and a Bachelor in Economics, both from the University of Hannover.
Lana Josipović
Lana JosipovićAssistant Professor, Department of Information Technology and Electrical Engineering
ETH Zurich
Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in 2022, she received a Ph.D. in Computer Science from EPFL. Her research interests include reconfigurable computing and electronic design automation. She is an Associate Editor for IEEE TCAD and ACM TRETS, and served as general, program, and topic chair of several international conferences and workshops. She is a recipient of the EDAA Outstanding Dissertation Award, EPFL Doctorate Award, Google Ph.D. Fellowship in Systems and Networking, Google Women Techmakers Scholarship, and Best Paper Award at ISFPGA'20.

From Software Programs to Digital Circuits

High-Level Synthesis (HLS) compilers enable programmers to automatically generate hardware designs from high-level software abstractions instead of writing tedious and time-consuming low-level hardware descriptions. However, today’s HLS compilers are still accessible only to expert users and for particular classes of applications; generating good-quality circuits still requires peculiar code restructuring and extensive experimentation with the tools. In this talk, I will discuss the challenges and limitations of current HLS approaches. I will outline an alternative HLS technique that overcomes these limitations and achieves high parallelism in general-purpose software applications. Finally, I will share my vision on future advancements of HLS and hardware design.

Sandip Kundu
Sandip KunduProfessor, Department of Electrical & Computer Engineering
University of Massachusetts Amherst
Sandip Kundu is a Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst. Recently, he also served as a program director at the National Science Foundation. Kundu began his career at IBM Research as a Research Staff Member; then worked at Intel Corporation as a Principal Engineer before joining UMass Amherst as a professor in 2005. He has published 300+ research papers in VLSI design and test, holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science, Senior International Scientist of the Chinese Academy of Sciences, and was a Distinguished Visitor of the IEEE Computer Society. He has been an Associate Editor of IEEE Transactions on Dependable and Secure Computing, IEEE Transactions on Computers, IEEE Transactions on VLSI Systems, and ACM Transactions on Design Automation of Electronic Systems. He has been Technical Program Chair/General Chair of multiple conferences, including ICCD, ATS, ISVLSI, DFTS, and VLSI Design Conference.

Hardware Alchemy for Machine Learning Acceleration

Machine learning is fueling a new hardware revolution. CPU, GPU, and FPGA manufacturers, and even memory and storage companies, are all in a race to create specialized hardware that accelerates machine-learning tasks. Even major machine-learning service providers like Google and Amazon are developing their own hardware solutions.

Next-generation cyber-physical systems, such as self-driving cars, rely heavily on machine-learning for perception, requiring real-time performance that demands hardware acceleration.

However, acceleration means different things in different contexts. This can be seen in the contour of various emerging solutions. This talk will explore the common denominators across various machine learning techniques and how hardware is being leveraged to accelerate them today.

Michael Schaffert
Michael SchaffertSenior Vice President Engineering E/E Architecture, Robert Bosch GmbH
Dipl.-Ing. Michael Schaffert studied electrical engineering at the Technical University of Stuttgart. In 1998, he joined Bosch in Stuttgart as hardware development engineer for Engine Control Units. 2001, he joined ETAS GmbH in Stuttgart as a Product Manager for Rapid Prototyping system. He left ETAS 2011, when he was Director for Product Management and Development and responsible for all ETAS HW. After ETAS Michael became Vice President at BOSCH and was the Head of Center of Competence for Vehicle Electrics and Electronics Architecture. In this role he was responsible for future E/E-Architecture’s development incl. responsibility for recognizing and assigning new technologies. In 2015 he moved to BOSCH Japan and was the Head of Customer Engineering responsible for Asian Pacific Engine Control Units & SW Service Business. In 2019 he came back to Germany and became Head of HW Development for Powertrain Control Systems BOSCH. In 2020 he was founding member of the new BOSCH Division XC (Cross-Domain Computing Solutions) and had the role as the head of Product Group responsible for Base-SW and Middleware incl. OS Product & Services. Since 07/2022 he joined BOSCH Semiconductor as a Senior Vice President responsible for System Engineering.

Enabling an Open Eco-System for Chiplet based Automotive SoCs

The automotive industry is currently witnessing an unprecedented surge in performance demands, surpassing the limitations set by Moore's Law. This surge can be attributed to several key factors, including the evolution of software-defined vehicles marked by centralized architectures and a heightened level of functional integration. Additionally, advancements in assisted and automated driving technologies have propelled the industry forward. Notably, the escalating demand for an enriched customer experience within the automotive sector has become a driving force behind the need for increased performance.

With the every-increasing performance demands of automotive, the integration of Chiplets-Based System-on-Chip (SoC) is emerging as a tangible reality. Traditional approaches, such as board-level integration (involving the integration of smaller specialized SoCs on a single PCB) and chip-level integration (constructing more advanced monolithic SoCs), are encountering inherent limitations. Now a pivotal question arises concerning the role of chiplets in the automotive context: Will they be closed vendor-specific or open up to a diverse, multi-supplier ecosystem?

The window of opportunity to shape the future of Automotive System-on-Chip (SoC) is now. Immediate actions are necessary to open automotive high performance SoCs designs for innovation and differentiation. Lowering entry barriers for new market innovations is essential, as is enabling scalability in the development of System-on-Chip (SoC). Defining standards for system behavior becomes crucial to improving interoperability, ensuring a comprehensive automotive life cycle. Moreover, fostering a market with multiple suppliers is integral for enhancing diversity and fostering healthy competition. Strategic approach - Embracing the Chiplet Advantage We propose to proactive embrace and shape the future of chiplets in automotive.

And more...