Neuromorphic-based System-on-Chips for Intelligent Brain-computer Interfaces

Neuromorphic system-on-chips are emerging platforms to satisfy the increasing demands on computing engines at very-low power consumption. In addition to various embodied applications such as robotics and self-driven cars, medical devices mainly brain-computer interfaces (BCIs) are frequently applied to efficiently address complex neurodegenerative diseases. Neuroelectronic approaches are facilitating the introduction of various wearable and implantable BCIs, which are intended for closed-loop neuromodulation. The later requires fast and very low-power miniaturized systems in particular when are intended to reside under the skull. Implemented to continuously monitor, treat and predict diseases evolution, a typical BCI includes a front-end sensing module, followed by neuromorphic processing unit for biomarkers location and decision making, followed by back-end actuators. We cover in this talk multimodal interfaces and implantable platforms grouping dedicated biosensing techniques including massively parallel neurorecording channels, followed by custom neuromorphic processing engines and a back end microstimulation stages. For these systems’ implementation and validation, we deal with multidimensional design challenges such as security, reliability, safety, self-powered operation, and high-data rate wireless telemetry. Several vital functions, such as addictions, vision enhancement, language decoding, and seizure detection and prediction, will be presented.

CMOS Lab-on-a-chip for Mass Production of Affordable Diagnostic Chips

Lab-on-a-chip is a technology which changed the traditional way by which biological samples are inspected in laboratories during analysis. This technology promises many advantages including better and improved performance, portability, reliability and cost reduction. A Lab-on-a-chip is composed of three main parts; actuation, sensing and electronics. Typically, hybrid technologies are used for the three parts, representing difficulties in integration and increased cost. However, Complementary Metal Oxide Semiconductor (CMOS) technology allows the functional integration of all parts including sensors, signal conditioning and processing circuits using a single homogeneous technology to develop a fully integrated lab-on-a-chip. CMOS technology is a very well-established mass production and cheap technology. Hence, any viable lab-on-a-chip based on CMOS technology will have direct commercial value and application. This talk presents the general aspects and components of a CMOS Bio-chip and illustrates the trends with specific examples of the speaker’s research and other existing research. Moreover, this talk summarizes the challenges and the future trends in CMOS based lab-on-a-chip technology.

Global Semiconductor Strategies and Chiplet Innovations 

In response to significant geopolitical shifts in recent years, major regions—including the United States, Europe, and South Korea—have launched substantial initiatives to strengthen their domestic semiconductor ecosystems. Through significant strategic funding programs, these efforts aim to reduce reliance on foreign supply chains and address critical vulnerabilities in chip design and fabrication. An overview shows latest activities as well as opportunities and challenges. A special focus will be placed on the fast-moving frontier of chiplet technology—a paradigm that promises improved scalability, design flexibility and long term cost reduction. We’ll examine its technical advantages, implementation hurdles, and the broader commercial implications for global competitiveness.  

The Importance of Chip Design from a European Perspective and the Role of Open-Source

Chip design accounts for approximately 40% to 50% of the total semiconductor value chain. However, Europe faces a significant gap in its chip design capabilities. As a result, numerous initiatives across Europe are aiming to strengthen design competence, education, and research in this field. In this context, open-source hardware is gaining increasing momentum within the design community. In this talk, we will introduce “Chipdesign Germany”, a national initiative to foster innovation in chip design. We will explore the role of open source, provide a comparative analysis of state-of-the-art open-source design flows, and discuss key challenges they face. Finally, we will present the evolution of our open-source DRAM modeling framework, highlighting its development journey and impact on the research and design ecosystem.

Optimization is a Keyword in System on Chip Design

The always increasing transistor count in modern chips, as well the exploding number of devices connected to the internet of things, is demanding new design approaches. One fundamental issue and challenge is the design optimization, mainly power optimization. In some applications, as implantable devices, reliability and power optimization is fundamental. It will be done a short overview of some techniques for power optimization at different levels of abstraction. But the main focus will be related to the physical design optimization, as it is becoming an important issue, not only for power optimization, but also for connections and vias optimization, increasing routability as well reliability. It will be shown some techniques and examples of optimization at physical design level.

Designing Real-Time Perception Models for Integration into Automotive SoCs

Enhancing pedestrian intent prediction is critical to the safe integration of assisted and autonomous driving systems, particularly in complex or adverse environments. This talk presents a high-performance, edge-optimized AI framework that fuses an image enhancement pipeline with a transformer-based network using self-attention mechanisms to achieve robust, real-time inference under challenging conditions. Designed with efficiency and integration in mind, the system is built to run on embedded platforms with strict constraints on latency and power consumption. The ultimate goal is to design and integrate this framework as a dedicated system-on-chip (SoC) component, enabling seamless deployment within the vehicle’s onboard perception and decision-making architecture. Validated on the JAAD dataset, the model achieves state-of-the-art accuracy with minimal inference delay, showcasing the potential of SoC-based AI acceleration to transform safety and perception in next-generation intelligent vehicles.